Abstract Preview

Here is the abstract you requested from the DPC_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Logic Assy on Interposer for TSV
Keywords: TSV, Assembly, Die Stacking
This paper presents the development status overview for large die assembly of 3D packages with TSV bearing silicon interposers and logic devices at Amkor Technology. Combining discrete silicon devices and their attendant functionality onto a silicon interposer has garnered a great deal of interest in the high performance community, driven by considerations such chip to chip bandwidth, lower latency and even lower power. Interposers with silicon fab back-end routing density and new ultra fine pitch copper pillar joining techniques promises to offer a timely performance stepping stone for high performance devices, who in some cases are now finding that the incremental performance benefit from advancing transistor performance alone is less that gratifying. The design motivations and tradeoffs for taking this bold step are reviewed and their influence on assembly technologies. Assembly process and supply chain alternatives to achieve this offering are reviewed and discussed. Technical process development challenges along the way are briefed, as well as the materials selection criteria and reliability testing results.
Mike Kelly, Sr. Director, Advanced Interconnects
Amkor Technology
Gilbert, AZ

  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems