Here is the abstract you requested from the IMAPS_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|VSECURE: VLSI Standby Subthreshold Leakage Current Reduction Technique|
|Keywords: static & dynamic power dissipation, leakage current, LECTOR|
|Scaling of transistor feature sizes has provided a remarkable advancement in silicon industry. With decrease in size leakage power dissipation becomes major concern for VLSI designers. According to the ITRS, while the performance increases due to scaling, the power density increases substantially every generation due to higher integration density . This directly affects performances of battery operated devices such as PDAs.Since this devices are substantially idle for majority times, it causes static power loss hence battery loss. A comprehensive survey and analysis has been done in development of various methods effective in reducing the static leakage power of portable devices. In this work we proposed a novel circuit technique that contributes in reducing leakage current in idle mode of operation. We cross compared our proposed technique with established techniques like stack Transistor, Sleep keeper, LECTOR etc. using fair experimental setup. Following this with help of comprehensive analysis our proposed method (VSECURE) is one of the optimum solutions over existing methods. Circuit parameters such as propagation delay, dynamic power dissipation, and static power dissipation form the basis of evaluation. The inverter followed by NAND gate is implemented and characterized for the aforementioned performance metrics. There after, the surveyed techniques are implemented over this Inverter and NAND gate and evaluated with the same performance metrics. The results of analysis are clearly shows that proposed method (VSECURE) is found efficient against reduction of Leakage power. In VSECURE we succeeded to reduce static power dissipation by 97% dynamic power dissipation by 83 % with delay penalty of only 7% as compared with base case. Simulation is performed using TANNER EDA tool for technology node 90 nm Predictive Technology Model.|
|Vaibhav Neema, Lecturer
Devi Ahilya University, Institute of Engineering and Technology
Indore, MP 452017,