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Mobile Device Passive Integration from Wafer Process
Keywords: RF, SiP, Passive Integration
In this paper, we will present some passive components made from silicon substrates (so called IPD process) and integration schemes using these components for RF applications. RF decoupling capacitors from this process will be compared with discrete SMD capacitors on ESR and ESL performance. Advantage and disadvantage of thin-film capacitors will be presented. Functional blocks (filters, baluns, diplexers, matching) made from the IPD process have shown good electrical performance and small form-factors. But due to physical size limitation, Q factors of IPD inductors are not as high as those from LTCC or laminate substrates. Q factor of an inductor is in general proportional to the size it occupies. To achieve better Q, larger size is required. Performance degradation due to the limited Q from the IPD process will be carefully investigated, and its impact on system performance will be justified with size reduction. Design approaches in order to minimize the negative impact will be also introduced. The thin profile from IPDs (could be100um-150um thick) makes them very suitable to be embedded inside laminate substrates. SiP or modules using this approach will have significant size reduction because they can be implemented directly under the active chips. The low profile of IPDs results in less cross-talk between the IPDs and the nearby parts (chips, SMDs, and traces), and therefore it is easier to maintain signal integrity. Because of the thin profile and the small form-factor features, IPDs are also well suitable to be used in SiP package. For RF packages, such as power amplifier front-end modules and transceiver modules, RF functional blocks and some decoupling capacitors and resistors may be integrated in big pieces of IPDs. These IPDs then may be implemented in side-by-side or stack-die configurations for SiP packages. Some case studies will be presented to demonstrate the advantages or favorite spots using the IPD technology, in terms of size reduction and electrical performance.
Kai Liu, Senior Engineering Manager
STATS ChipPAC Ltd.
Tempe, AZ
USA


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