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SerDes Design and Modeling over 25+ Gb/s Serial Link
Keywords: 25 Gb/s serial link, SerDes, Modeling
In this paper, signal integrity challenges for high speed serial link at 25 Gb/s, such as lossy channel, noisy environment and high speed circuit design will be discussed. A few potential solution spaces to address those challenges are investigated. It will be demonstrated that improved signal integrity and advanced signal processing enables 25 Gb/s performance in next generation systems. Joint system design optimization is required to achieve reliable operation across backplanes and cables for 25+ Gb/s links. Modeling methodologies used in SerDes behavioral models like IBIS-AMI to ensure good correlation with transistor level circuit and silicon will be also introduced. At the end, SerDes performance with discussed signal processing technologies over short reach, long reach and extra long reach 25 Gb/s serial links will be simulated using behavioral model.
Cathy Liu, Sr. Manager, SerDes Architect
LSI Corporation
Milpitas, CA

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