Here is the abstract you requested from the IMAPS_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|AUTHOR WITHDREW 8-18-11: Stacked-Die Multichip Package for Memory|
|Keywords: fan-up RDL , Wafer level package, memory die stack|
|AUTHOR WITHDREW 8-18-11: Multichip modules (MCP) and System in Package (SiP) are widely used in mobile devices for their small footprint and light weight design. Both NAND flash cards and DRAM memory modules are using such types of packages in embedded memory and storage applications. A new concept for memory MCP and SiP packages using a novel, flip chip stacked die assembly is presented. Such die stacks use no TSV (through silicon via), no wire bonds, and no substrates. They can be regarded, therefore, as a new 3-D wafer level package with “fan-up” interconnections, or FU-WLP. The fabrication process is similar to a fan-out WLP and can thus be processed on either a reconstituted wafer or a suitable panel. After the initial dice (logic IC, controller) are embedded in the wafer or panel, a three-dimensional build-up RDL (redistribution layer) is fabricated using thick photoresist and plated copper pillar posts as via for vertical interconnect. The final RDL structure contains a sufficient number of layers to match that of the dice in a stack, each having exposed pads for bonding to its mating chip. For identical memory chips, each die is placed above the lower one slightly offset such that its I/O bumps on one side are bonded to the exposed pads on the RDL structure. The designs for a 2-die and a 4-die stack MCP and SiP will be described in detail. Sacrificial probe pads may be built-in for in-process test. After stacking, final molding is applied to the wafer. Following the appropriate form factor, a finished wafer may be singulated to form individual eMMC CSP packages, or flash cards (uSD, SD) with gold finger I/O contacts.|
|Wei Koh, PhD, Chief Technologist
Powertech Technology Inc. (PTI)