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Evaluation of Package-Induced Mechanical Stresses using a Stress-Sensitive Testchip
Keywords: package-induced stress, testchip, MEMS
A semiconductor die typically undergoes a variety of assembly processes. Those processes tend to alter the mechanical stress distribution, which the semiconductor die is exposed to. While high stresses may cause evident package- or die cracks, lower stresses might still deteriorate the electrical performance of the device significantly – in particular in the field of MEMS and sensor devices. We report on a stress-sensitive testchip and its application to characterize the stress impact of certain assembly processes onto the die. The testchip contains an array of individual test cells, each of them consisting of a CMOS current mirror circuit enabling the determination of a stress distribution across the chip area. The stress measurement system is based upon two piezoresistive MOSFET channels being aligned along different crystal directions and thus revealing different piezoresistive properties. Ideally, with zero external stress exposure, these transistors show exactly the same current gain. This situation changes when stress is applied, allowing the electrical determination of absolute in-plane normal stress values σxx, σyy as well as the shear stress distribution σxy. We demonstrate excellent reproducibility of the test system as well as its sensitivity to relative changes in mechanical stress load within a range of ± 3 MPa. The methodology is applied to different package concepts, in particular targeting pressure sensors. Casting and curing of encapsulating expoxy material for instance, increases the stress level by one order of magnitude, while die- and wire-bonding tend to play a minor role. Moreover, small changes in the package concepts, which at a first glance might be considered negligible, alter not only the magnitude of the stress field, but also its effect on spatial variations of device parameters across the die. Eventually, this methodology shall transform into a useful tool for the development of low-stress concepts and stable product designs.
Horst Theuss, Principal Backend Development
Infineon Technologies
Regensburg, Bavaria 93049,
Germany


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