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Making Intelligent Tradeoffs Between SI, PI and EMI
Keywords: SI, PI, EMI
Old email as of 7-29-11 (amolak_badesha@agilent.com) Now will Avago Technologies - P: 510-825-9555; amolak@gmail.com. The trend of ever-increasing data rates and pressure to reduce cost is having significant impact on PCB, Package and High-Speed System design. More and more data signals are being cramped in smaller spaces. Proper power and ground planes are a luxury many designers do not have. As a result, SI, PI and EMI design is becoming more challenging. To further complicate things, a design that is optimized for SI or PI may be really bad for EMI. This requires that the designers make intelligent tradeoffs between SI, PI and EMI design targets. In this paper, we'll show a design methodology that shows how to simulate and optimize for SI, PI and EMI all at the same time, so that proper design tradeoffs can be made.
Amolak Badesha, Senior Application Expert
Agilent Technologies (left Agilent on 7-29-11) Now with Avago Technologies - amolak@gmail.com - P: 510-825-9555
Santa Clara, CA
USA


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