Here is the abstract you requested from the IMAPS_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|An Investigation of Passivation Layer and Via Formation Process for Fine Pitch Substrate|
|Keywords: WLP, passivation, coating|
|Recently the package market is demanding the smaller package size and the lower impedance electrical path with a short interconnection. These demands are required for not only also package, but organic substrate design technology. Currently, the technology is able to take over 30um line and 30um space design. So newly substrate design technology should be investigated to realize fine line and space. The wafer level chip scale package (WLP) process is one of them, which has the solution of the market demands above. It had advantages of fewer processing steps, lower cost, and enhanced device performance. However, WLP process is not accepted on the organic substrate because it was designed for wafer level process. In particular on WLP process the passivation layer was coated by spin coating method and via hole formed by photo exposure. In the case of organic substrate process, the passivation layer was laminated by SR or ABF and via hole formed by laser drilling. In our study, to realize organic substrate with fine line and space, the passivation material was chosen by photo-sensitive material and micro-via was formed by using photo exposure. To coat the photo-sensitive passivation on organic substrate, slit die coating method was chosen instead of spin coating or SR (or ABF) lamination. To optimize the coating method, many parameters was optimized, for example pattern thickness, coating speed, dispensing rate, etc.|
|Jin-Gul Hyun, Engineer
Samsung Electro-Mechanics Co., LTD.
Suwon, Yeoungtong-Gu 443-370,