Here is the abstract you requested from the IMAPS_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Electrical Performance of Advanced Surface Laminar Circuit in High-End FCBGA Applications|
|Keywords: Power Integrity, Signal Integrity, Advanced Surface Laminar Circuit|
|Advanced Surface Laminar Circuit (Adv-SLC) is a build-up substrate technology designed to satisfy the requirement of the most advanced semiconductor chips. Adv-SLC is featuring a low Coefficient of Thermal Expansion (CTE) of 10 ppm/degC that reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. It is also featuring a fine pattern of 10 um in line width and spacing, plated through-holes of 150 um in pitch and micro-vias of 25 um in diameter. These high-density features enable significant size reduction of substrate. Power integrity has been recognized as important part of entire electrical design in high-end systems such as a server where increase in data transfer rate has been a critical issue. FC-BGA technology has been implemented as a preferable solution in such systems, and build-up substrates have been commonly used. The key to a high performance system is enhancement in electrical performance in the FC-BGA substrate, and the reduction in substrate size and thickness will play an important role. This paper introduces high power and signal integrity achieved by the Adv-SLC technology comparing to those achieved by the current technology. The high wiring capability in the Adv-SLC can reduce the number of layers to 10(4-2-4; 2 signal and 6 power/ground layers) from 16(6-4-6; 4 signal and 12 power/ground layers) in the current technology, with having significant improvement in power and signal integrity. The improvement of the loop impedance is attributed to both the reduction of substrate thickness and the high density placement of Z-connections such as micro-vias and plated through holes. The improvement of the cross-talk noise is due to the reduction of distance between signal and reference plane.|
Kyocera SLC Technologies Company
Yasu, Shiga 520-2362,