Here is the abstract you requested from the IMAPS_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Advanced Semiconductor Packaging Solutions: From QFN to BGA, 3D WLP|
|Keywords: advanced packaging, nantong fujitsu, china|
|With continued demand for semiconductor component to be higher in performance, smaller in size, advanced packaging technology has been developed and progressed rapidly in past decade. With more silicon value moving to the package, it opens up a possible supply chain value change. IDM, wafer foundries, packaging house, and material supplier all poised to take on more values in this new era. This presentation reviews Nantong Fujitsu's advanced packaging technology development activities with some examples. By feature of structure, we refer the advanced package mainly to: • lead frame based QFN/DFN package, with option of Cu Wire; • stack die CSP, flip chip BGA , system in package and package on package; • wafer level CSP and flip chip bumping. While researching and developing high performance package construction and optimizing manufacture process, we have put a focus on low cost and high quality in production as well. Recent efforts on those area include copper wire bonding, low cost flip chip package and wafer level package solution to replace laminate substrate. Furthermore, with increased level of system integration, chip-package-board co-design approach becomes essential to further optimize system performance and reduce product cost.|
Nantong, Jiangsu 226006,