Here is the abstract you requested from the IMAPS_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Fully Additive Chip Packaging: Science or Fiction?|
|Keywords: additive, 3D integration, packaging|
|In advanced IC packaging and interconnects, there is a trend towards an ever increasing degree of integration combined with a high level of production flexibility. Integration is needed, both on chip scale (3D-stacking) and on system/product scale (integrated interconnects). Technically, these product requirements call for manufacturing challenges such as low-cost integrated (3D) interconnects, mask-less processing, fast prototyping, short tool transition times and wafer-level packaging. To address these future challenges in a flexible manufacturing setting, TNO has developed a fully mask-less process based upon additive manufacturing, to build 3D interconnected structures using micro stereo lithography (µSLA). The process comprises a building step in insulator material directly from a Computer Aided Design (CAD) file followed by global metallization, molding and trimming of the interconnects. To demonstrate the potential of such additive processes, a fully functional sensor with four chips integrated on bare die- level has been built. Experimental results are demonstrated and discussed. It is shown that based on the µSLA process, it is possible to generate a working sensor circuit with 3D-interconnects that show a conductivity more than adequate for building electrical systems. Also, it is shown that the metallization has a quality that complies with common interconnect technologies such as wire bonding or flip chip. Application domains are elaborated, based on a cost model for the current process as well as for additive mask-less manufacturing in general. Thus, the industrial potential of µSLA as a manufacturing process will be assessed. It is shown that this process is eminently suited for high density 3D integrated systems. The process allows for quick and cheap production of small series down to single products by changing nothing but a software file that describes the package and interconnect structure.|
|Gerrit Oosterhuis, System Architect
Eindhoven, Noord Brabant 5600 HE,