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Feasibility Study of a 3D IC Integration System-in-Packaging (SiP)
Keywords: 3D IC integration, TSV, Interposer
The feasibility study of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) passive interposer with RDL (redistribution layer) on both sides, IPD (integrated passive devices) and SS (stress sensors). This interposer is used to support a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and then overmolded on its top side for pick and place purpose. The bottom side of this interposer is attached to a 2-layer organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). The interposer and all the chips have been fabricated from a 12” (300mm) multi-project wafer (MPW). The TSV diameters are 10μm and 15μm and on 40μm and 50μm pitches. The thickness of the interposer is 100μm and all the chips is 50μm. First, the stress sensors are fabricated by a simple implantation method. After the routine via formation and front-side metallization, the MPW is temporarily bonded with a supporting wafer. After back-grinding the composite wafers to expose the TSVs, it is followed by back-side metallization/UBM (under bump metallurgy), and microbumping. After de-bonding to remove the supporting wafer, all the chips (with lead-free microbumps) are singulated from the MPW and are chip-to-wafer (C2W) bonded to the interposer in the 12” MPW. The challenges such as the thin-wafer handling, microbumping, underfilling, overmolding, and C2W bonding of the 3D IC SiP made from the 12” wafer and the ways to overcome them have been reported. The important index such as S-parameters, thermal resistance, and stresses in the interposer and all the chips have been measured and characterized. Also, reliability assessments such as the thermal cycling tests (-40↹125oC, dwell and ramp times = 15 min) of the microbumps between all the chips and the interposer, the ordinary solder bumps between the interposer and the organic substrate, and the solder balls between the organic substrate and the PCB are ongoing. All these data will be analyzed and reported before the manuscripts are due.
John H. Lau, ITRI Fellow
ITRI
Hsinchu, Taiwan 310,
R.O.C.


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