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Equivalent Thermal Conductivities and Design Guidelines for Through Silicon Vias (TSVs) in 3D IC Integration
Keywords: Equivalent thermal conductivity, 3D IC intergration , TSV
Thermal management is one of the critical issues of 3D IC integration. Thus low-cost and effective thermal management design guidelines and solutions are desperately needed for widespread use of 3D IC integration. Even with the most effective software and advanced high-speed hardware, it is impossible to model all the TSVs in a 3D IC integration system-in-package (SiP). Thus, equivalent thermal conductivities for TSVs are urgently needed. In this investigation, a set of empirical equations of equivalent thermal conductivities (k) in the in-plane (xy) and cross-plane (z) directions has been developed to characterize the thermal behavior of 3D IC integration with TSVs filled with copper. A finite volume model of single TSV with copper redistribution layer arranged in a via-in-pad (VIP) format is created at first and the model is analyzed using ANSYS Icepak simulation software. The parametric study comprises of TSV diameter (D), TSV pitch (P), silicon chip thickness (H) and SiO2 dielectric/passivation thickness (t). The results show that: (1) the empirical equations of equivalent thermal conductivities in the in-plane direction (kxy) are a function of SiO2 thickness (t); (2) kxy is a function of (D/P); and (3) the empirical equations of equivalent thermal conductivities in the cross-plane direction (kz) are a function of (t/H) and (D/P). The errors of both sets of equations are within 10% range when compared with the simulation results for the TSVs with 5μm < D < 50μm, 0.2μm < SiO2 < 2μm, 0.1 < D/P < 0.75, and H > 20μm. The data analyses show that: (a) the thickness of SiO2 dielectric/passivation layer has significant effect on the thermal behavior of TSV array due to its low thermal conductivity; (b) in most cases, the copper filled TSVs enhance significantly the equivalent thermal conductivity in the cross-plane direction (kz); and (c) on the other hand, the copper filled TSVs has less effect on kxy. In addition, based on the present parametric study and results, a set of design guidelines for optimizing the thermal performance of TSVs in 3D IC integration has been proposed.
Jack Heng-Chieh Chien, Engineer
ITRI
Hsinchu, Taiwan 310,
R.O.C


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