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Optimization of SiO2, Barrier/Seed Layers, and Cu Plating for a 300mm Wafer
Keywords: Cu plating, SiO2 deposition, Barrier layer
Through silicon via (TSV) is the most important key technology for 3D IC integration, which brings the advantages of reducing form factor and increasing system operation speed. Cu metallization with damascene technique has been widely applied in the TSV filling owing to its high electrical conductivity, high throughput and low cost. However, there are some challenges for TSV Cu filling technique. First is the requirement of thick enough SiO2 insulating layer and Cu diffusion barrier layer. Insufficient insulating layer could induce electrical leakage and insufficient barrier layer could cause degradation in dielectric layers and further breakdown of devices. For Cu plating process, the Cu plating-residue, which is also known as overburden on top of the wafer, prefers to be thin and the dimple profile is requested (by CMP requirements) to be as flat as possible. From economy points of view, the improvement of throughput and cost for TSV filling is important. Therefore, ways to shortening the extremely long Cu plating and seed-layer PVD processes are proposed. In isolation liner study, oxide deposited by PECVD with TEOS precursor is used because of its low sticking coefficient. Process temperature is kept lower than 250oC to minimize the thermal impact to the device. Process pressure, mass flow of TEOS and oxygen are the variables for optimizing the step coverage of oxide liner in 10μmx60μm TSVs. The step coverage is 16.9% at bottom and 10.3% at bottom corner positions where the minimum thickness occurred. The self-ionized plasma (SIP) PVD system is used for Ta barrier and Cu seed layer deposition in this study. For sputtering deposition, the energy given to metal ions has large impact on step coverage especially for deep vias. And in this study, the two important energy-related parameter, plasma power and substrate bias, are investigated. For the Ta barrier results, it shows that the large amount of metal ions in plasma produced by higher plasma power will diminish the Ta step coverage. On the other hand, the higher bias power will enhance the Ta step coverage due to the attraction of electric field caused by substrate bias. Through this approach, the best parameters for PVD Ta barrier deposition have been obtained and the minimal Ta step coverage of 10μmx60μm TSVs can reach 20%. Besides, the efficient reduction of Cu seed-layer thickness with continuous Cu seed deposition also attains. Voids-free TSV filling is carried out by multi-step copper plating. Based on the fixed additive concentration, plating with DC current density switches from small to large step by step. The good bottom-up power lets plating time less than 45 minutes. Attribute to the good surface inhibit ability and well recipe controlling, 1.8μm plating overburden (total surface copper is 3.8um including 2μm Cu seed layer) has been obtained. Besides, the performance of 1μm to the good surface inhibit ability and well recipe controlling dimple profile makes it feasible for CMP process. Based on the current experimental results, a set of process guidelines for optimizing isolation liner, barrier layer, seed layer, and copper plating has been proposed.
L. Wu, Engineer
Hsinchu, Taiwan 310,

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