Micross

Abstract Preview

Here is the abstract you requested from the IMAPS_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

High-Quality Multiple Global Layers on Chip-Redistributed Wafer for Wafer-Level System Integration using Pseudo-SOC
Keywords: pseudo-SOC, chip-redistributed wafer, resin shrinkage behavior
This paper reports advanced process technology to realize high-quality multiple global layers on chip-redistributed wafer for wafer-level system integration using pseudo-SOC. The authors have been developing pseudo-SOC technology by which KGD chips are integrated to a chip-redistributed wafer using high-rigidity epoxy resin and global layers with interconnecting chips are formed on it. They have established the basic process for pseudo-SOC, and integration of MEMS and LSI, or front-end RF LSI and passive components, has been demonstrated. However, the first stage of pseudo-SOC technology was based on a single global layer consisting of insulating layer and conductive layer, which limited the range of application. In order to expand its application toward system-level integration, it is necessary to realize high-quality multiple global layers. Therefore, the following critical issues remain: 1) each process should be achieved at low temperature to withstand resin-based materials; 2) resin curing shrinkage should be controlled to ensure positioning accuracy; 3) throughout the process, warpage of the chip-redistributed wafer should be suppressed. For these issues, first, they selected epoxy resin optimized the glass transition temperature and the content of filler and polyimide for insulating layer to allow low-temperature curing process as a base material. Then the curing shrinkage behavior of resin was systematically investigated, considering a volume ratio of total chips in chip-redistributed wafer and an effective control parameter to reduce the chip displacement was identified. In addition, effective measures to decrease the warpage at each process were implemented. As a result, high-quality multiple global layers were obtained by total optimization of warpage throughout the process. Based on these results, realization of more than five-stacked high-quality global layers for wafer level system integration using pseudo-SOC was achieved. Application of this technology for pseudo-SOC packaging of RF systems and sensor modules is also presented.
Atsuko Iida, Research Scientist
Toshiba Corporation
Kawasaki, Kanagawa 212-8582,
Japan


CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems