Micross

Abstract Preview

Here is the abstract you requested from the IMAPS_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

AUTHOR WITHDREW 8-11-11: Remateable Conductive Ball-in-Pit Interconnects for Chip Powering and Alignment in Proximity Communication Enabled Multi-Chip Packages
Keywords: Proximity Communications, 3D Interconnect, Chip powering
AUTHOR WITHDREW 8-11-11: Proximity Communications (PxC) based on capacitive, inductive or optical signaling is a promising technology for low-power, low-latency, and high bandwidth-density chip-to-chip communications. In a simple PxC package, two chips (“islands”), attached to a substrate, may be interconnected via a third chip (“bridge”) that attaches face-to-face with the islands, is powered directly by them and communicates off-chip solely via PxC. Such a planar packaging approach may be extended to build large-array multi-chip packages containing several islands interconnected by PxC-enabled bridge chips. Any practical implementation of such a PxC-enabled package requires a complementary interconnect solution for powering the bridge chips. Additionally, PxC demands tight alignment between overlapping PxC I/O pairs to minimize signal loss and channel crosstalk. We present a novel interconnect technology, called Conductive Ball-in-Pit (CBiP) that can simultaneously power bridge chips via the island chips, and enable self-alignment between packaged chips. The CBiP structure comprises high-precision metalized inverse pyramidal pits microfabricated at the wafer-scale in designated matching locations on the chips to be assembled. The pits on one layer are then populated with conductive microspheres (diameter ≥100μm). During assembly, the bridge chip need only be placed within half the ball diameter for the chips to self-align and be locked into position laterally. An external clamp can then be used to hold the chip-stack and also provide force for a compression electrical contact. As, the CBiP is not a permanently attached interconnect, chips may be swapped out with repeatable high-accuracy alignment. We have successfully demonstrated electrical conduction between chips using CBiP interconnects in a 3-chip test-vehicle. The CBiP interconnects were measured to have a low resistance of 57mOhm and able to carry >1.5A of dc current. In another experiment, a bridge chip was measured to self-align within 2μm of the target location. The details of test-vehicle design, fabrication and characterization are presented in this paper.
Hiren D. Thacker, Principal Hardware Engineer
Oracle Labs
San Diego, CA
USA


CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems