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|High Performance Multi-Layer Board Considering Compatibility with Fine Pitch Package|
|Keywords: Fine-pitch board design, CPW structure, Return path with mesh holes|
|Recently, the fine-pitch BGAs and chip scale packages have been developed to meet the strong demands in the mobile consumer market. A significant advantage of using fine-pitch and chip scale package is the efficient use of space in the application board. Moreover, it is contributed to achieve the densely increase of I/O ball counts with the chip-stacking technology. Most mobile products have offered small form factor that incorporated the Integrated Circuits via these packaging technologies. The multi-layer boards have supported to electrically connect components through the conductive signal line and via-holes. One of the main problems for the multi-layer boards is an extremely small space between the pads for FBGA package balls. Another is the limited diameter of mechanical drill determined by the total thickness of multi-layer board. Normally, the fan-out design method has been known as the good method to escape these limitations of fine-pitch board. As electrical performance of devices is continually improved, it is not easy to achieve the higher signal quality through only fan-out design. Therefore, it has been focused on the multi-layer board with the higher electrical performance and compatibility for fine pitch packages. This paper will discuss the new design method to overcome the difficulties to give effect to the multi-layer boards. The coplanar waveguide (CPW) with specific mesh holes has been developed as a high performance transmission line in which all the conductors including the signal and return paths are placed on the same plane. It is the most effective wave to overcome the limited drill diameter to minimize the total thickness of multi-layer board. The proposed board with high performance and compatibility with fine pitch packages was designed and fabricated. Moreover, we have successfully demonstrated the electrical evaluation through the write/read operations of mDDR2 that contain the most severe operating conditions.|
|Ki-Jae Song, Design Engineer
Asan, Chungcheongnam-Do 336-851,