Abstract Preview

Here is the abstract you requested from the IMAPS_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

3D-Stacking of UTCPs as a Module Miniaturisation Technology
Keywords: 3D-stacking, UTCP, TH-interconnection
3D-stacking of Ultra Thin Chip Packages (UTCP's) – one of the emerging technologies in the field of high density integration is presented here. This technology is developed to increase the functionality of the electronic devices and to raise the comfort zone by reducing the overall size and weight of the package. This has a bright future in the area of mobile communication, medical equipments like hearing aids, implants, patient monitoring. But it is challenging to obtain a stacked module of almost same size as of a bare die with four times as much data storage capacity. The above said process involves ultra-thin chip package (UTCP) technology to produce miniaturized modular packages, followed by stacking and through-hole (TH) interconnection technology. UTCP technology is a board level packaging concept, based on embedding of ultra-thin chips (~20 µm) within two 20 µm thin spin-on polyimide layers resulting in a thin flexible chip package of ~50 µm thick. Precise placement of chips on the base substrate facilitates the industrial level production of multiple UTCPs on a single panel. A fan-out metallization on the package aids testing before integration, solving the KGD issue. Stacking of the 4 layers of UTCPs by using 25 µm thick layers of adhesive films and vacuum lamination processes results in stacked UTCP modules of total thickness ~320 µm. The connection to the different layers of the UTCPs is realized by drilling THs on the outer contact pads on the stacked packages, followed by metallization of these THs by Cu electroless deposition, electroplating and finally metal structuring. This technology has been successfully implemented for the production of 3D-stack of 4 EEPROM memory dies.
Swarnakamal Priyabadini, Ph.D. Student
Centre for Microsystems Technology, Affiliated with IMEC vzw
Gent, East Flanders 9052,

  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems