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The Road Towards Fully Hybrid CMOS Imager Sensors
Keywords: CMOS imager sensor, processing, CuSn bump process
Monolithic imagers contain the photosensitive elements as well as the read-out IC (ROIC) on the same substrate. Backside thinning on (permanent) carrier enables efficient collection of photo-generated carriers through back illumination, resulting in almost 100% fill factor. This contrary to front side illumination where light loss is introduced due to reflection on metal interconnects. Together with an optimized backside ARC coating, high quantum efficiency (QE) can be achieved. Hybrid imagers consist of a detector array which is produced separately and hybridized on a read out IC. A fully-hybrid backside illuminated imager has more flexibility because the detector array and the ROIC can be separately optimized to the needs of the application leading towards further improvement on QE and cross-talk. Backside thinning and processing has been carried out using innovative processing techniques on 200 mm wafers making use of temporary carriers, which completely avoid the need for direct handling and processing of very thin wafers. Fully processed thinned diode arrays were flip-chipped onto the ROIC by means of a Indium bump per pixel [1]. The Indium bump process has however limited fab compatibility. In this paper we will also focus on a high yielding electroplated CuSn micro bumping process. For hybrid imagers very dense bump interconnects are needed. Each unconnected bump will show up in the image as a black dot. Therefore investigation of the interconnection yield is critical. A dedicated test design contains very long daisy chains of 1766 CuSn bumps between the top and bottom die. The bumps are 10µm in diameter with a 20µm pitch. In total, the 2cm x 2cm large dies consist of about a million bumps. We report an average daisy chain yield above 90% for the CuSn die-to-die assemblies. The obtained yield on the daisy chains implies a defect density that is below 60 for 1 million bumps. Processing aspects like choice of plating seed layer, the influence of cleaning agents and seed layer etchants on the micro bump performance are being discussed. Thermal reliability analysis is ongoing. [1] J. De Vos et al., “Processing aspects to achieve high-end hybrid backside illuminated imagers”, IMAPS, Research Triangle, 43rd International Symposium on Microelectronics, 2010.
Joeri De Vos, Senior Process Integration Engineer
IMEC
Heverlee, Vlaams-Brabant 3001,
Belgium


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