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Assessments and Characterizations of Stress Induced By Via-First TSV Technology
Keywords: stress, TSV, via-first
Through Silicon Via (TSV) is a key enabling technology for 3D stacking. One of the main concerns regarding the TSV introduction inside the IC fabrication is the resulting stress build up in the silicon substrate that may induce warpage or expansion at the wafer level, crystalline defects in the neighbouring silicon of the TSV and finally can impact performances and reliability of the CMOS devices as well. Polysilicon, tungsten and copper are the three main conductors that are considered for the TSV fabrication. In a first part of this paper the different factors that contribute to the stress in the TSVs including the geometry, the materials and the process will be reviewed. Then, we will show results on how the stress is built up in the substrate during the fabrication of the TSVs and the influence of some of the specific process steps like the insulation and the filling of the vias. Simulated data will be also presented and compared to experimental findings. After bonding on a temporary carrier and thinning of the substrate to expose the vias the stress built up during the fabrication of the TSV can be revealed by the expansion of the silicon membrane. The choice of the bonding material is shown as some critical point of the process integration. We also present some characterizations of silicon defects by chemical revelation around the TSV structures. The impact of thin wafer expansion on TSV electrical performances will be then presented. Finally we show that with the optimization of some key process steps, stress induced in via-first technology may be acceptable for IC integration.
Gabriel Parès, Project Leader
CEA-LETI
Grenoble 38054,
FRANCE


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