Here is the abstract you requested from the IMAPS_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Quality and Reliability of 3D TSV Interposer and Fine Pitch Solder Micro-Bumps for 28nm Technology|
|Keywords: TSV, interposer, micro-bump|
|Silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. Furthermore, providing high wiring density interconnections and improved electrical performance are the reasons TSV interposer has emerged as a good solution and getting too much industry attention. High density three dimensional (3D) interconnects formed by high aspect ratio through silicon via (TSV) and fine pitch solder micro bumps are presented in this paper. Several DOEs and design/material optimizations were performed in order to yield high aspect ratio void-free TSV copper via and reliable micro-bumps. Quality and reliability of copper TSV and micro-bumps are monitored in-situ during the process. This paper presents some of the quality and reliability results as well as micro-bump and TSV resistance data. Furthermore, bake and thermal-cycling measurements are presented to insure reliability of the design and the material selected for the 28nm technology TSV interposer FPGA.|
Los Altos, CA