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|Wafer Bumping and Characterization of Fine-Pitch Lead-Free Solder Microbumps on 12” (300mm) Wafers|
|Keywords: Micro bump, Lead free, 3D TSV|
|Solder microbumps are one of the important enabling technologies for 3D IC integration. The ordinary solder bumps (~100μm) are too big for 3D IC integration SiP (system-in-package) applications, which require much smaller solder bumps (≦20μm). In this study, lead-free solder micro wafer bumping of 300mm wafers with two different chips is investigated. The dimensions and characteristics of these chips are: (1) 18mm x 22mm with more than 7,300 pads on 170μm and 340μm pitches, and (2) 10mm x 10mm with more than 2,800 pads on 50μm and 150μm pitches. The pad size and passivation opening of both chips are 25μm and 20μm, respectively. In order to perform characterization and reliability assessment of the solder micro bumps/joints, both chips are with interconnected between pins in an alternating pattern so as to provide a daisy chain connection when the micro bumped chips are soldered to a TSV (through silicon via) passive interposer. After pattern trace formation, the microbumps have been fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness (Ti = 50nm / Cu = 120nm) has been designed and applied to minimize the undercut (< 1μm) due to wet etching but still achieved good plating uniformity (bump height variation < 10%). IMC thickness vs. number of reflows and shear strength vs. several agings have also been obtained and discussed. The Cu-Sn lead-free solder micro bumped chip has been bonded on a Si wafer (chip-to-wafer or C2W bonding). Also, the micro-gap between the bonded chips has been filled with a special (very small filler size) underfill. The bonding and filling integrity have been evaluated by shear test, open/short measurement, SAT analysis, and cross-section with SEM analysis.|
Industrial Technology Research Institute (ITRI); Electronics & Optoelectronics Research Laboratory
Hsinchu, Taiwan 31040,
R. O. C