Micross

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Development of IMC Bonding with Wafer Level Underfill Process for 3D-IC
Keywords: Wafer Level , 3D-IC, TSVs
We performed stacking experiments on Si dies using annular tungsten TSVs (Through Silicon Vias) and Cu studs with low-volume solder micro-bumps. Unlike standard 100-micron C4 (Controlled Collapse Chip Connection) solder bumps, very small solder volumes (< 6 microns in height) form IMC (InterMetallic Compounds) in the die to die junctions. Silicon die stacking with low-volume solder interconnection is an attractive method for 3D integration. The formation of intermetallic compounds increases the strength of the solder joints and its melting point. It offers such benefits as extension to fine-pitch integration, increased vertical heat transfer and hierarchy for repeated thermal processes without re-melting. However the joints formed by intermetallic compounds can be brittle and less resistant to mechanical stress as compared to the joints mostly formed by pure solder. The joint's mechanical properties play an important role in the system's reliability. Therefore in-depth evaluations of joint's mechanical properties are crucial to further advance this technology. In this report, we conducted the thermal cycle tests on the silicon die stack mounted on an organic substrate with the two joint metallurgies(Cu/Sn and Cu/Ni/In). The deep thermal cycle tests showed that the Cu/Ni/In joint systems have less failures than the systems with Cu/Sn joints. The energy dispersive X-ray (EDX) analyses of the solder joints after the 2000 cycles of thermal cycle tests showed that the CuSn intermetallic compounds dominate the Cu/Sn joint whereas the region of mostly pure indium region still remains in the Cu/Ni/In joints even after the tests. We also conducted a finite element analysis of the Si die stack with the Cu/Sn joints on an organic substrate. The analysis showed that increasing the Si interposer thickness can reduce stresses in the intermetallic compound joints. On the other hand, the die to die gap of IMC bonding is too narrow to fill an epoxy resign material by the standard capillary underfill process. OBAR (Over Bump Applied Resign) technique, which is a waferlevel underfill process developed by IBM, is one of solution to fill the resign in such a narrow gap. A filled resin is applied over the bumps of a wafer and dried or b-staged. The b-staged wafer is diced. A singulated, OBAR coated chip is aligned to a substrate and joined by melting the solder bumps. We also discuss OBAR process and material for ultra narrow die to die gap.
Yasumitsu Orii,
IBM Research Tokyo
Yamato-city, Kanagawa-ken, 242-8502,
Japan


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