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Quantitatively Predicting the Reliability of Complex Integrated Circuits
Keywords: Physics of Failure, Failure Mechanisms, Predicting
Modern electronics typically consist of microprocessors and other complex integrated circuits (ICs) such as FPGAs, ADCs, and memory. They are susceptible to electrical, mechanical and thermal modes of failure like other components on a printed circuit board, but due to their materials, complexity and roles within a circuit, accurately predicting a failure rate has become difficult, if not impossible. Development of these critical components have conformed to Moore's Law, where the number of transistors on a die doubles approximately every two years. This trend has been successfully followed over the last two decades through reduction in transistor sizes creating faster, smaller ICs with greatly reduced power dissipation. Although this is great news for developers of high performance equipment, including consumer products and analytical instrumentation, a crucial, yet underlying reliability risk has emerged. Semiconductor failure mechanisms which are far worse at these minute feature sizes (tens of nanometers) result in higher failure rates, shorter device lifetimes and unanticipated, early device wearout. Physics-of-Failure (PoF) knowledge and an accurate mathematical approach which utilizes semiconductor formulae, industry accepted failure mechanism models, and device functionality can access reliability of those integrated circuits vital to system stability. Currently, four semiconductor failure mechanisms that exist in silicon-based ICs are analyzed: Electromigration, Time Dependent Dielectric Breakdown, Hot Carrier Injection and Negative Bias Temperature Instability. Mitigation of these inherent failure mechanisms, including those considered wearout, is only possible when reliability can be quantitatively calculated. Algorithms have been folded into a software application to not only calculate a failure rate, but also give confidence intervals and produce a lifetime curve, using both steady state and wearout failure rates, for the IC under analysis. Furthermore, the algorithms have been statistically verified through testing, employ data and formulae from semiconductor materials (to include technology node parameters), circuit fundamentals, transistor behavior, circuit design and fabrication processes. Initial development has yielded a user friendly software module with the ability to address silicon-based integrated circuits of the 130 and 90nm technology nodes. DfR is now working to extend the capability of the tool into smaller technology nodes (i.e. 45nm) and other material sets such as silicon on insulator (SOI). Several commercial organizations have indicated a willingness to assist with the development and validation of 45nm technology through IC test components and acquisition of field failure data. Continued development would incorporate this information and would expand into functional groups relevant for analog and processor based integrated circuits. The initial work was performed by DfR Solutions, and funded by Aero Engine Controls, Boeing, GE, NASA, DoD, and FAA in cooperation with the Aerospace Vehicle Systems Institute (AVSI).
Ed Wyrwas, Member of the Technical Staff
DfR Solutions
College Park, MD
USA


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