Micross

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Layer-to-Layer Alignment and Bridge Powering in a Silicon Photonic Macrochip Package
Keywords: silicon photonic interconnect, multi-chip package, alignment
We present the packaging architecture of a CMOS-Photonic “Macrochip” -- a logically-contiguous piece of silicon that combines multi-core processors and dense memory via an ultralow-energy CMOS-photonic interconnect network. Also described within are two key innovations that address the issues of chip-to-chip alignment and chip-powering that are especially central to building an optoelectronic multi-chip package. The former is achieved via our ball-in-etch-pit technology and has allowed demonstration of submicron layer-to-layer alignment. For the latter, we introduce a novel interconnect technology called Conductive Ball-in-Pit (CBiP). Each CBiP interconnect comprises a conductive microsphere sandwiched between high- precision metalized inverse pyramidal pits on two face-to-face assembled chips; the interconnect has a self- alignment quality, and achieves electrical conductivity via a remateable compression contact.
Hiren D. Thacker, Principal Hardware Engineer
Oracle Labs
San Diego, CA
USA


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