Here is the abstract you requested from the OPTO_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Thermal Tuning Efficiency Optimization of the Waveguide Ring Filters in SOI CMOS|
|Keywords: silicon photonics, thermal design, silicon micromachining|
|Silicon photonic circuits have shaped up into a compelling technology offering to boost energy and performance for computing, signal processing and communication systems. Ring waveguide resonating structures with high quality factors are the key components servicing silicon photonic links. It has been widely recognized that the operating wavelengths of fabricated ring resonator optical components, such as modulators and filters, invariably differ from their design values. There are multiple sources leading to this difference originating in process variability, manufacturing tolerances as well as in wafer thickness variations, notably the silicon device layer of the SOI structure. All of these affect the fabricated ring's critical dimensions to a different degree which the ring's optical propagating mode is very sensitive to. Silicon is characterized by a high thermo-optic coefficient such that rings made in silicon can be tuned in its resonating wavelength with a change in temperature by the use of thermal heaters in the direct vicinity to the ring waveguide. Thermal tuning therefore could be utilized in order to compensate for the described fabrication variations and appropriately match the ring devices in the photonic link to each other and to their light sources. Tuning power should be appropriately accounted for in overall the link budget and ultimately minimized. In this paper through rigorous numerical analysis we analyzed the key structure parameters leading to highly efficient spectral tunability of the microphotonic ring structures manufactured in commercial 130 nm SOI CMOS technology. Optimized structures of our ring devices resulted in their maximized thermal impedance and increased efficiency of the thermal tuning of their operating wavelength. An overall 20x increase in the tuning efficiency has been shown in the simulation and validated by experiment in the post-processed waveguide structures by co-integration with bulk silicon micro-machined structures relative to their original performance with an intact substrate.|
|Ivan Shubin, Principal Hardware Engineer
San Diego, CA