Here is the abstract you requested from the OPTO_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Design and Wafer-Level Fabrication of Positive Self-Alignment Structures for Improved Vertical Optical Coupling|
|Keywords: self-alignment, proximity I/Os, heterogeneous integration|
|Optical proximity communication has been recently proposed by Oracle Labs and offers significant power, latency and area savings over traditional interconnects. However, it has been shown that the performance of optical interconnects, in general, depends strongly on one's ability to control the relative placement of chips involved very accurately; for the optimum performance, the gap between chips must be minimized in a controlled manner, and two chips also need to be kept parallel and laterally aligned. Traditional assembly methods are inadequate for this application as it results in relatively large gaps and also it lacks ways to control the relative position of the chips accurately. We present a low-cost self-alignment structures that address these issues; at the core of the technology is wafer-level batch fabricated half-dome like structure at the four corners of one chip; the dome structure can be made of polymer or metal, and it is 150µm in diameter and 50µm in height. On the second chip, inverse pyramid pits are etched in the complementing positions. When two chips are brought together and placed on top of each other so that the half dome structure fits into the pit, the structure will self-align the chips to submicron accuracy in all six degrees-of-freedom. The relative position of the pair of chips including lateral position, tilt and the gap are controlled just by modifying the relative dimensions of the pit. Most importantly, the gap between chips can also be minimized to less than few microns. The dome structure is a surface micromachined wafer-level process that uses reflowed polymer as the sacrificial layer and it can be fabricated post-CMOS (and other devices) on wide range of substrates to enable heterogeneous integration between a CMOS IC and a non-silicon based photonics chip. Critical to the fabrication of the structures are techniques used to control the uniformity of the shape even after using inherently poorly controlled processes such as polymer reflow and electroplating.|
|Hyung Suk Yang, Student
Georgia Institute of Technology