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Removing Passivity Violations in Via Modeling with Improved Impedance Calculation for an Infinitely Large Parallel-Plane Pair
Keywords: parallel-plane impedance, passivity, via modeling in printed circuit boards
In multilayer printed circuit boards, vias can significantly affect the transmission of high-speed signals. An effective approach has been developed to model via structures for signal and power integrity, which includes via-to-plane capacitances and parallel-plane impedances (usually infinitely large plane pairs are used for fast estimations). However, it is found recently that the via model can lead to potential passivity violations. To addrss this issue, an improved impedance definition is applied to an infinitely large plane pair, and new calculation procedures are developed. With the improved impedance calculation, it can be shown that the potential passivity issues can be eliminated.
Dazhao Liu, Student
Missouri University of Science and Technology
Rolla, MO
USA


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