Abstract Preview

Here is the abstract you requested from the SysPack_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

ASIC Performance Improvement by Redesigning Its Package
Keywords: package, simultaneous switching noise, crosstalk
The electrical performance of an ASIC (Application-Specific Integrated Circuit) is related to not only the circuit level design in die but also the package level design, which includes the design and analyses of power integrity and signal integrity. In this paper, the transient power noise on the 1.8V IO power supply of an ASIC is reduced around 30% by redesign its package and the crosstalk between signal paths inside the package is decreased about 40%. The new design significantly improves the electrical performance of the ASIC and results in higher reliability when compared to its original design. In the new design, an additional solid plane for the VDDO18 is added above the core except for the partial plane inherited from the original design on its original layer, which makes the loop inductance of the power rail seen by the die minimized. The crosstalk is reduced by moving some traces on the original signal layers in the old design down to the new signal layer in the new design. It is beneficial to use a thin core in the new design instead of a thick core in the old design. The thin core makes the PTHVs short. In consequence, it reduces the DC IR drop. For a given percentage of DC IR drop on a certain power rail, this reduction means less number of PTHVs are needed to maintain the same amount of DC IR drop on the power rail. Therefore, more power and ground vias can be added to reduce loop inductance in the new design with a think core package. In addition, VIPPO technology is used in the new design to minimize the loop inductance introduced by the interface of package and PCB.
Jianmin Zhang, SI Engineer
Cisco Systems, Inc.
San Jose, CA

  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems