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|Analytical Modeling of Coupled TSVs in 3D ICs|
|Keywords: signal integrity, through silicon via, parasitic extraction|
|Power delivery and dissipation are the primary limiters of performance and integration in CMOS scaling. Conventional 2D integration technologies are also limited in terms of bandwidth. 3D IC integration provides a path for power reduction and improved bandwidth in electronic systems. 3D IC integration technology and silicon interposers at the present rely on through silicon vias (TSVs) for vertical interconnections. The improvement in power and bandwidth by adapting a 3D integration methodology therefore depends on the electrical properties of TSVs. This paper presents analytical formulas to extract an equivalent circuit model for coupled through silicon via (TSV) structures in a 3D integrated circuit. We make use of a multiconductor transmission line approach to model coupled TSV structures. TSVs are embedded in a lossy Silicon medium, hence they behave as metal-insulator-semiconductor (MIS) transmission lines. The models we present can accurately capture the transition between slow-wave and dielectric quasi-TEM modes, which are characteristic for MIS transmission lines, as well as the metal-oxide- semiconductor (MOS) capacitance. The results are validated against 2D quasi-static simulations and 3D full-wave electromagnetic simulations. The derived equivalent circuit models can easily be applied in circuit simulators to analyze crosstalk behavior of TSVs in a 3D integrated system. The main contribution of this work is the development of an analytical TSV model that captures the MOS capacitance effect, slow-wave and dielectric quasi-TEM modes, and full RLGC coupling terms in an array of TSVs.|
|A. Ege Engin, Assistant Professor
San Diego State University
san diego, CA