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Design Challenges for 3D Packaging
Keywords: 3D IC, stacked chip, 3D IC packaging
Due to the increasing density, performance and cost requirements for modern semiconductor devices we have seen an explosion of new packaging technology, primarily focused on stacking in the ‘vertical' direction or what we are referring to as 3D. Chip stacking has been in practice for many years, but only recently has the technology been considered for mainstream production. The use of stacking technologies has progressed from camera modules for cell phones, to same-type memory chips stacked in many different orientations (allowing wire bonding to the package), to through-silicon via and other methods of vertical interconnect. These techniques improve density by thinning the stacked die to maintain low profile height and improve electrical performance by maintaining short electrical length paths for signals. These technologies increase the electrical performance and reduce space use dramatically. On the other hand, the challenges for 3D design are vastly changed from single-chip or traditional multi-chip module / hybrid methods. The difficulty in electrical, thermal and mechanical design becomes more profound when the chip stacks are meant to create a complete system-in-package with mixed die. This presentation intends to highlight challenges in design for 3D stacks, ‘traditional' and TSV applications and provide an overview of measurement, modeling and implementation needs.
Thomas S. Tarter, President
Package Science Services
Santa Clara, CA
USA


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