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Effect of packaging miniaturization on heat sinking COTS processors
Keywords: miniturized packaging, bare die integration, system design
Significant investment in low power processing has enabled numerous long lifetime handheld and battery-powered devices in the past five years. At the same time, packaging technology has evolved such the miniaturization technologies of some high end approaches outpace the miniaturization of the integrate chip in relative terms. This drives a thermal issue – the manufacturer-recommended heat sink for high-power operation takes up approximately 30x more footprint than the chip itself and precludes the insertion or negates the effectiveness of some of these packaging technologies. This paper will compare a candidate commercial off-the-shelf (COTS) processor packaged and heat sinked in a conventional arrangement versus a bare-die component with ultra dense packaging technologies. It is an effort to reduce the effective footprint – chip plus heat sink – of a processor to take advantage of miniaturization trends in the packaging domain without resorting to extraordinary thermal approaches such as microfluidic boiling. As a case study, we consider a high-end Intel Atom processor, which generates 13 W over a footprint less than 1 cm2. We leverage packaging technology to increase the effectiveness of alternate heat paths such as direct chip-to-board sinking to reduce the relative thermal load on the top side heat sink. By removing flip chip ball grid array (FCBGA) interfaces and implementing ultra-thin interconnect integration technology; heat can be dissipated to other components such as the thermal back plane of the board. This reduces the effective footprint of a processor and/or can increase the number of processors that interface to a given sink. While the thermal design is always application specific, we propose a formalized comparison of the thermal consequences of conventional vs. high end miniaturized packaging.
Brian Smith,
Draper Laboratory
Cambridge, MA

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