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Package Development for Bottom PoP with Large/Thin Die
Keywords: Thin , PoP, Stacking
PoP (Package on Package) technology has been used in portable electronics (primarily mobile phone) for a few years now. Business case for PoP such as logistical advantages, cost of ownership etc. have been well documented. Mobile phones in general and smart phones in particular have faced continuous pressure for integration of functions such as camera, GPS, high end graphics, etc. This, in turn is putting updward pressure on die size for devices such as applications processor, which typically is the bottom package in a PoP stack. At the same time, there is downward pressure on the overall height of the PoP stack (processor + memory) due to the “thin is in” design philosophy for portable consumer electronics such as tablets and smart phones. The ‘lethal' combination of large and thin die is proving to be a tremendous challenge for PoP (BTM) package design and manufacturing. This problem is compounded by the ever reducing ball pitch which reduces the warpage (coplanarity) specifications for the device making it even more difficult to meet the specification consistently in high volume manufacturing. The paper will introduce some of the materials and methods (such as FEM) used to identify the possible solutions to the issue of warpage control of large/thin PoP packages while at the same time trying to meet (max) height specifications for next generation PoP stacks. Various design and material properties that are the disposal of the packaging engineer/designer will be explored and their impact on package warpage (at both room and high temperature) will be presented. Particular emphasis will also be placed on the interaction of the variables and the various engineering tradeoffs will be presented.
Suresh Jayaraman, Director, Advanced Package Development
Amkor Technology
Chandler, AZ
USA


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