Here is the abstract you requested from the TT_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Through Silicon Via (TSV) in Mobile Applications|
|Keywords: CSP, Bump, Wafer support system, wafer finish, thermal compression bond (TC-Bond)|
|Through silicon via technology has offered a paradigm shift in mobile applications by providing performance improvements in both speed and power dissipation. The improvement in memory bus bandwidth by use of wide I/O memory has proven to be very effective in addressing memory latency issues. In the case of mobile applications, the memory die is stacked in vertical fashion on top of the applications processor in either a pre-stacked cube format or singularly to provide a finished package with an extremely thin vertical footprint. The benefit of stacking the ultra thin memory in this format allows for not only latency improvement, but also opportunity for reduced system-level cost by optimizing system partitioning and removing embedded DRAM from the core logic and reconfiguring as stackable DDR memory. The benefits of through silicon via and die stacking are clear. The technology required to package these devices however is not yet settled. There is significant development still underway to try to achieve robust processing with high quality outputs. For mobile applications the stacking of high speed memory directly to the backside of TSV bearing logic devices is anticipated to become the standard for years to come. This packaging technology requires new manufacturing techniques however. Dual side processing of TSV bearing wafers is new to the semiconductor industry. Key to dual side wafer processing is the backside of wafer processing, more commonly known as wafer finishing. Much of the wafer finishing processes technology is still maturing. Since the wafers thickness requirement for logic devices is ≤ 100 µm in most cases, ≤ 50 µm or less in all memory applications, wafer support systems are required to allow processing of wafers down standard bump lines. From the wafer finishing perspective the industry remains divided. There exist two primary business cases for wafer finishing today. One path has wafers delivered to the OSAT in their fully finished state, with the Foundry or IDM completing the backside finishing. In this scenario, the wafers are shipped to the OSAT at their final thickness of ≤ 100 µm for most logic devices and ≤ 50 µm for most memory devices. An alternate path however, provides wafers that are shipped at full thickness to the OSAT and the TSV backside finishing is completed as part of the assembly flow process at the OSAT. Most foundry, fabless or IDM companies prescribe to one flow or the other however. They prefer that either the finishing of wafers occurs at the foundry or IDM, or the finishing of the wafers occurs at the OSAT. More companies seem to be leaning towards wafer finishing at the OSAT as opposed to the foundry or IDM. The OSAT companies, in either case, must be able to operate in both spaces creating additional challenges to the OSAT. Wafer finishing requires backside processing of the TSV bearing wafers including revealing of the TSV through thinning operations, re-passivation of the thinned wafer, and pad formation over the TSV tips or possibly even redistribution on the backside in limited cases. For the OSAT these choices are tailored to address the many different die interfaces encountered. The wafer finishing choices plays a significant role in ability to package the die together through die stacking techniques. For mobile products the typical package configuration requires the memory to be placed on top of the logic die (applications processor), with a final over-molded finish to protect the stacked die. The memory die may be a singular die or multi pre-stacked die composite supplied by a memory company. In most cases, assembly of the mobile products begins with logic die attachment to an organic substrate. This attachment can take two paths, with either a traditional mass reflow flip chip assembly process using capillary underfill or a fine pitch copper pillar thermo compression bonding (TC-Bond) process using non conductive paste. The final attachment of the memory die to logic die would then follow using a fine pitch copper pillar TC-bond process. In either case, warpage management plays a critical role in providing a robust high yielding process. It is important to note there are many possible assembly paths which can be taken for mobile products today. Below is a list of the most prominent approaches: • Die to substrate • Die to die • Die to wafer In this paper, the focus is on the following packaging aspects of TSV technology in high end mobile products: • Wafer Finishing of TSV Bearing Wafers • Thin Wafer Handling • Assembly of Ultra Thin Die • Long Range Roadmap|
|Ron Huemoeller, Sr.VP, Advanced 3DIC