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Effects of Package Pitch and Thickness Reduction on Board Level Reliability
Keywords: Thin Package, Fine Pitch, BLR
Smaller and thinner hand held products with increased functionality continue to drive package size reduction in all dimensions and/or ball pitch reduction to accommodate more I/Os in a similar size package. For wafer level chip scale packages (WLCSP) such as Amkor's CSPnl and CSPn3, ball pitch reduction can enable die size reduction and thereby significant cost saving as the number of die per wafer dramatically increases without sacrificing the I/O count. The die size reduction can also provide improved drop performance due to a reduce distance to the die center neutral point and finer pitch may enable adding of mechanical no connect balls in the critical die corner pad locations. Thinner package also offer an advantage in drop performance due to increased package flexibility. There are, however, some perceived disadvantages of package thickness reduction and pitch reduction. Thinner package invariably requires thinner die with possible negative impact on package warpage. Similarly, smaller ball pitch results in the use of smaller ball sizes and ball pad openings which might result in lower board level reliability. Over the years, Amkor has collected board level reliability data for same size but higher I/O count CSP and WLCSP packages both under temperature cycling and drop conditions. Data has also been collected on BLR performance as a function of package thickness. Similarly, simulations have been performed to understand how packages with higher ball count but smaller ball pitch compare with the same size package using larger ball pitch and size. This paper provides a summary of test and simulation results for CSP and WLCSP packages and identifies important factors that affect board level reliability.
Ahmer Syed, VP - APD/Mech Engineering
Amkor Technology
Chandler, AZ
USA


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