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Challenges for Thin Wafer Level Packaging
Keywords: WLP, CSP, Fanout
Wafer Level Packaging (WLP) began as an extension of Flipchip Bumping, and has grown into a major packaging technology for mobile applications. The first commercially available WLP was Wafer Level Chip Scale Packaging, where Solderballs were applied directly to the die, with no lead frame or substrate interposer. This packaging concept has been successful primarily because of the size reduction that has been possible over alternative packaging technologies. WLCSP has been a true Chip Scale Package (CSP), as the lateral dimensions of the package are as small as is possible, being the same as the die itself. Although WLCSPs are also often thinner than alternative packages, they have usually been 0.5mm thick, or thicker. Over the past few years, that has been changing, as customers are asking for thinner and thinner WLCSPs for compact mobile devices. Wafer Level Packaging has also been expanding into technologies and capabilities beyond the basic WLCSP. These include Fanout WLPs, MEMS WLPs, Integrated Passive WLPs, and 3D WLPs with TSVs. All of these variations in WLPs are also being driven to thinner and thinner package dimensions. Each of these WLPs has challenges as we attempt to take them to the thinner dimensions being asked of them. Some of the challenges are inherent in the material sets, and some are related to the processes and/or handling capabilities. These often require the development of new material sets and/or processes to successfully implement them. We will review some of these challenges as we go forward with demands from the mobile electronics industry for thinner and thinner final Wafer Level Packages.
John Hunt, Director of Engineering
ASE US, Inc.
Tempe, AZ

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