Here is the abstract you requested from the Automotive_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Thermal Performance and Reliability of Bonded Interfaces|
|Keywords: Bonded Interfaces, Sintered Silver, Reliability|
|In automotive power electronics packages, conventional thermal interface materials such as greases, gels, and phase change materials pose a bottleneck to heat removal and are also associated with reliability concerns. There is an industry trend towards high thermal performance bonded interfaces. However, due to coefficient of thermal expansion (CTE) mismatches between materials/layers and resultant thermomechanical stresses, there could be voids and crack formations in these bonded interfaces, as well as delaminations which pose a problem from a reliability standpoint. These defects manifest themselves in increased thermal resistance in the package, which acts as a bottleneck to heat removal from the package. Hence, the objective of this research is to investigate and improve the thermal performance and reliability of novel bonded interface materials for power electronics packaging applications. In this work, we present results for thermal performance and reliability of bonds/joints based on thermoplastic (polyamide) adhesive, with embedded near-vertical aligned carbon fibers as well as silver sintered material. The results for these two materials are compared to conventional lead-based (Sn63Pb37) and lead-free solder (Innolot) joints. These materials are bonded between 50.8 mm x 50.8 mm footprint silicon nitride substrates and copper baseplate samples. Samples of the substrate/baseplate bonded assembly undergo thermal cycling from -40°C to 150°C according to Joint Electron Device Engineering Council (JEDEC) standard Number 22-A104D for up to 2000 cycles as an upper limit. The dwell time of the cycle is 10 minutes and the ramp rate is 10°C/minute. Damage occurrence is monitored after every 100 cycles by several nondestructive techniques - including acoustic microscopy and high-voltage potential testing. Defect formation (voids, cracks, delaminations) can be detected via the imaging techniques and these defects could potentially increase the thermal resistance of the interface or the substrate/baseplate assembly. The high-voltage potential testing characterizes the integrity of the ceramic substrate.|
National Renewable Energy Laboratory