Here is the abstract you requested from the DPC_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Innovative 3D Polymer Packaging and Multi-Stacking of Integrated Circuits|
|Keywords: SiP, 3D-Interconnect Technology, Packaging 3D, Vertical Vias|
|The packaging technology is one of the key technologies to improve industrial challenges as increased performance, miniaturisation or weight reduction of components. In recent decades, special attention is focused on SiP (System in Package) resulting from integration of several ICs issued from different technologies (RF, analog, digital and GaAs on Si) into a single "package". The largely used technology "Through Silicon Via (TSV) has serious drawbacks such as yields, difficulty of implementation etc.... In this work, a ‘Polymer Through Via' (TPV) technique for vertical stacking of ICs, proposed by 3DPLUS, has been developed. The principal objective is to increase the potentialities of the vertical staking (complex IC; multiple I/O...) of Si chips without loss of performance or yield. The technique used consists to surround the IC chips by using particular resin and to fill (with metallic films) the vertical holes drilled in this material. We have tested two approaches: SU8, a photosensitive epoxy polymer; and a commercial resin HYSOL® FP4511. The first experiments show interesting results for the two ways: it is necessary, firstly, to develop a global approach for each of them in order to reduce the thermal stress occurring during the technological process, secondly to insure the highest AR (Aspect Ratio ) coefficient of vias and finally to metalize them. For HYSOL® FP4511, we have used two types of pulsed laser (355nm Nd: YAG and Femto seconde IR 150fs) to realize holes with an AR = 33; for SU8, we have obtained AR=50 by pholithography techniques. Various metallisation methods have been used to ensure electrical continuity toward the vias connecting the four superposed IC. We expect to focalise our presentation by producing MEB photos and experimental results; we shall expose the advantages of this TPV technology and its future place in the so known ‘More than Moore' roadmap.|
|Sari Al Altar, Student