Micross

Abstract Preview

Here is the abstract you requested from the DPC_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

IC Package Route Planning Methodology Designs Better Products
Keywords: routing, design, planning
As package design complexity increases, and design cycle times are increasingly subject to aggressively truncated timelines, the need to achieve efficient one-pass physical routing of complex, I/O dense, IC packages becomes critical. Critical high-speed interfaces such as DDR2, DDR3, PCI Express, and HDMI now constitute a high percentage of signals in an electronic package. This presentation will focus on utilizing an integrated route-planning tool to quickly and effectively plan the physical layout of package design interfaces, without the expenditure of time and dedication of resources required to perform traditional routing iterations. Route-planning allows package design teams to easily communicate with customers and other engineering teams to make intelligent trade-off decisions for layer usage, space allocation, Power Delivery Network (PDN) solutions, signal referencing and Die-to-Pkg netlist feasibility and optimization.
William Acito, IC Package Design Product Engineer
Cadence Design Systems
Chelmsford, MA
USA


CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems