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3D Integration of RF Package
Keywords: RF Integration, 3D Integration, Interference and cross-talk
As form-factor has been one of the key drivers for mobile devices, 3D integrations that make the use of vertical dimension have been widely explored. Conventional side-by-side approaches, for implementing memory devices, controlling circuits, baseband devices, application processors, RF devices, etc., have been replaced by package-on-package (PoP) or other 3D approaches. One key issue for 3D approaches is to maintain signal integrity, which is typically not the bottle-neck for side-by-side solutions. For an RF stack-die package, where at least one of the chips in the configuration is RF chip, having either active or passive function, the interference or cross-talk between the chips in a package may severely deteriorate the signal integrity, and may make the package malfunction. In this paper, we will describe a RF stack-die package where a RF transceiver chip and an IPD chip are implemented. Chip-to-chip interference directly by individual components (e.g., between inductor coils in different chips), and through the power feeding lines (or power distribution networks) in the IPD chip and in the laminate substrate, is investigated. Based on this analysis, proper arrangement of the off-set between the two chips is applied in the final package design, and is approved to be able to overcome a receiver sensitivity issue occurred in the previous version of the package.
Kai Liu, Senior Engineering Manager
STATS ChipPAC, Inc.
Tempe, AZ
USA


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