Here is the abstract you requested from the DPC_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|3D-Integration: An Intermediate Solution|
|Keywords: maskless, packaging, interconnect|
|3D integration, using Though Silicon Vias (TSVs), of die is an area where a magnitude of developments is on-going worldwide. Yet it will take several years before 3D-integration technology has become a common approach. Nevertheless the market continuously asks for smaller, faster and more energy efficient systems, thus emphasizing the need for high density integration. Another trend is the change from extremely high volume production to more flexible production allowing for smaller series. Technically, such product requirements call for manufacturing challenges such as low-cost integrated (3D) interconnects, mask-less processing, fast prototyping, short tool transition times and wafer-level packaging. To address these challenges in a flexible manufacturing setting, TNO has developed a process-flow using a fully mask-less processes to print housing and support with 3D interconnect structures using micro stereo lithography (µSLA) in combination with a variety of printing technologies for the routing and interconnection of the die. The general approach is to build functional layers (e.g. sensing, processing, memory, energy, etc) using, one or more, off-the shelf semiconductor components, embed these assemblies using the mask less printing technologies. This embedding will also incorporate the vertical interconnection allowing the functional layers to be stacked to finally yield an integrated, miniaturized system. Experimental results are demonstrated and discussed. It is shown that, based on the µSLA process and other printing technologies, it is possible to generate a working sensor system build in a layered topology using vertical interconnections. Based on a cost model it will be shown that this approach allows for quick and cheap production of small-to-medium size series down to single products by changing nothing but a software file that describes the housing- and interconnect-structure and inserting the corresponding chips and devices.|
|Ben van der Zon, Scientific Manager
Eindhoven, Noord Brabant