Here is the abstract you requested from the DPC_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Package Stacking Effects on PoP Warpage at Reflow Temperature: Simulation and Practical Guide|
|Keywords: PoP(Package-on-Package), warpage, solder joint reliability|
|PoP(Package-on-Package) stacks consist of a bottom package containing a high performance logic device and top package containing high capacity or combination memory devices. System manufactures achieve lowest cost and maximum logistical benefits, when these two components are sourced from different IC device suppliers then stacked in the final board assembly flow. Thus, package stacking process is a key technology in order for system manufactures to be able to select the top and bottom components from various suppliers. The one of the critical factors for PoP reliability is large warpage at reflow temperature which makes open solder. To prevent these problems, the room-temperature warpage of PoP, which is measureable practically in mass production, is strictly controlled by using correlation between the room-temperature warpage and reflow-temperature warpage. The correlation, however, does not show consistency through logic and memory combination. Furthermore, the warpage from Moire measurement shows not only ui-modal but also bi-modal behavior in certain PoP stack. That means the location of open or short bump failure site does not limited to corner of center of package anymore. In this paper, a warpage model was developed to correlate the room-temperature warpage and reflow-temperature. And then, we suggested material selection and layout design guidelines to quickly optimize the warpage performance, especially on above issues.|
|Dong-Cheon Baek, Q & R Team
Samsung - Technology Quality and Reliability Group
Republic of Korea