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Glass Wafers as Carriers for Silicon Thinning Process
Keywords: 3D-IC, thinning , glass
As the industry strives to get more logic packed with the same power demand on the same footprint, the thickness of silicon device wafers needs to decrease, meanwhile its diameter increases. In the thinning process, the silicon wafer will be bonded face down to a carrier and then ground down to the desired thickness. After this process step, device wafer and carrier wafer will be separated again. Silicon wafers are often used for carrier wafers, but some engineered glasses have a number of attributes that make them well suited for use as carrier wafers. All carrier materials need to meet specific requirements including: strength to withstand handling; low particle and metal contamination; and a CTE matching the application's requirements. Non-uniformities in the carrier directly impact the accuracy of the silicon wafer's total thickness variation (TTV). Other important requirements include excellent flatness, high thickness uniformity, and low warp. Easy inspection of the bond layer and the use of advanced low temperature de-bonding techniques are also desirable for the large diameter silicon wafer precision thinning processes. We will demonstrate that glass can be engineered to be a good candidate for use as a carrier substrate and show how the strength of engineered glass wafers compares with silicon wafers using standard mechanical strength test methods. Even though the mechanics of failure differ greatly between crystalline materials (Si) and amorphous materials (glass), the data shows that the strength of a glass wafer compares favorably to the one of a silicon wafer. In addition, we will present data on CTE, flatness, warp, and TTV for glass wafers. The data will support the conclusion that engineered glass wafers represent an ideal candidate for carrier substrate in the large size precision silicon wafer thinning process.
Ilona Schmidt, Standards Engineering Manager
Corning Inc.
Corning, NY

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