Here is the abstract you requested from the DPC_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Keywords: thin packaging, thin substrates, flip chip|
|What does thin or ultra-slim packaging mean? That of course depends on the particular cross-section of the substrate e.g. single layer vs. double layer vs. coreless or embedded component substrate, etc. The thinnest prepreg based substrate and concomitant package is a single layer substrate termed a-S3 ™ and can be as thin as 90 µ and 400 µ, respectively, with the appropriate mold cap. The manufacturing concept for a-S3 has inspired a new manufacturing concept for thin prepreg based coreless substrates with any number of layers. Layers two through five have been demonstrated successfully. The practical layer count is limited only by yield and cycle time. The same concept has been extended also to embedding active die as well as passives, a-EASI™. The total package height here is governed by the thickness of the embedded elements. The simplest embedded substrate is a two layer substrate with a MOSFET die. The advantage is a very low profile power package with excellent electrical and thermal performance. The interconnections to the die/passives are formed by plated laser vias as is common practice. Process flows and concepts will be introduced here. Thin substrates do pose many challenges during substrate manufacturing as well as during assembly. Some of the handling concepts will be elucidated. Sample pictures will be shown to demonstrate successful builds and some reliability data will be presented as well.|
|Bernd K. Appelt, Director Busness Development
ASE US, Inc.