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Low Resistive Metallic Through Silicon Via For Silicon Interposer
Keywords: Silicon interposer, Silicon via, Via last
To meet the semiconductor and MEMS industry demands with high number of component IOs, shorter signal path, hermetic sealing, better impedance control and smaller foot-prints, the through substrate via interconnections becomes a key technology. Normally, the manufacturing sequence of a via last TSV (Trough Silicon Via) can be summarized as via formation by etching, followed by insulator, barrier and seed layer deposition, subsequent copper filling, wafer thinning and finally wafer/chip alignment, bonding and dicing. The process sequence for the presented AAC XiVIA via resembles that of an ordinary via last TSV, starting with the silicon oxidation, followed by lithography, etching of silicon dioxide, KOH etching of the silicon and subsequent Deep Reactive Ion Etching (DRIE) from one or both sides until the constriction is open. The seed layer is then sputtered onto both sides of the wafer, and a patterned resist mask for electroplating is deposited. The final steps include copper electroplating, resist strip and seed layer etching; the vias can either be open or closed depending on the requirements. The presented process have a few important differences from the ordinary via last TSV manufacturing technique; first, the metal in the vias is formed together with the conductor layer instead of in two different steps and second, the process does not include wafer thinning which facilitates wafer handling. Also, the copper plating time is substantially reduced. The via design and process sequence is based on today´s available equipment. The XiVIA has already been successfully applied for manufacturing of fine-pitch component interposers (for bare ACTEL FPGA ProAsic3E-3000 dies) at AAC Microtec and for hermetic sealing in Silex Microsystems Met-Cap, WLP solution. The following tests, corresponding to space environmental requirements, have been performed on a large set of vias and interposers and have passed 3sigma analysis: via resistance: < 10mOhm, deep thermal cycling: 500 cycles from -75°C to +150°C, extreme thermal chock: from -160°C to +125 °C, shear and pull fatigue test: passed 10 000cycles at 20MPa, mechanical vibration: passed 5 Hz to 2 000 Hz vibration spectrum according to ESA/Ariane 5 launcher specification, mechanical chock: passed 2 000 g in X, Y, Z direction.
Anders Ljunggren,
AAC Microtec
Uppsala,
Sweden


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