Here is the abstract you requested from the DPC_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|A Methodology for Chip - Package Interaction (CPI) Modeling in 3D IC Structures|
|Keywords: Chip-Package Interaction modeling, 3D Stacked IC, Design impacts on Stresses|
|Chip-Package Interaction (CPI) is a significant concern for modern electronic devices and this concern is magnified for 3D Stacked IC. Hard bumps, soft dielectrics, thin die and complex geometries of the stacked die require an ability to model and evaluate the interactions and risks. In packaged IC, dissimilar materials along with the thermal history during the assembly process results in significant residual stresses. These stresses can impact process yields, reliability and die electrical performance. Examples of these effects are ball cracking, ILD/ELK cracking or delamination and shifts in the behavior of sensitive devices such as transistors in analog circuits. Traditionally modeling and evaluation of these risks have been handled by different groups/companies (foundry, OSAT, Fabless Device Mfg) and have been hindered by the difficulty of using different tools and more importantly collaborating without revealing proprietary models and process information/recipes. In this paper we present a modeling flow which incorporates a seamless interface between the tools traditionally used for both package and silicon modeling. This is accomplished by utilizing Boundary Conditions (BC's) to act as a hand-off between the two simulation tools. A package level modeling approach is developed incorporating package assembly processes to predict residual stresses at the end of package assembly process. This package level simulator uses a nested sub-modeling approach for detailed extraction of stresses at different locations within BEOL layers of die, u-bumps, and C4 bumps from package level simulations. Additionally, it allows complete flexibility in selecting boundaries at chip-package interface and then the extraction of BC's necessary for die and transistor level simulations. These boundaries for Chip-Package Interaction are selected by the device manufacturer and the output from this simulation is fed into device level simulations. To provide flexibility for the user and to attain quick turnaround time, a web hosted interface is enabled to run package simulations online. The capabilities of this modeling approach are demonstrated by studying the impact of design and material parameters on stresses at various interconnect structures constituting a typical 3D IC stack package. An example of active silicon layer stress correlation from package level model and die-level model will be presented, thus validating this overall modeling flow.|
Amkor Technology Inc.