Here is the abstract you requested from the DPC_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|3D Packaging Solution Providing DDR & LPDDR Co-Support for Ultrabooks and Next Generation Servers|
|Keywords: DDR Memory, High Performance, DFD|
|Effective 3D stacking of DRAM devices can offer many benefits; improved performance, increased component density and greater surface area utilization. To enable the new generations of processors to reach their performance potential many manufacturers have developed more efficient interface formats that enable greater memory bandwidth. This revolution in performance driven electronic systems continues to challenge the IC packaging industry. The challenge is clear. To ensure that the memory functions are able to support the increased signal speed, product developers will need to explore more innovative 3D package assembly techniques and process refinement methodologies. The methodology selected for package assembly, however, must consider process complexity, the costs associated with each process, overall package assembly yield and, from the users perspective, end product reliability. For some applications companies have had limited success in stacking die elements directly onto an interposer substrate using wire-bond processes. High performance DRAM die, however, is especially difficult to stack. This is due to the center positioned wire-bond sites. This factor has complicated the DRAM die stacking process and because of the excessively long wire-bond interface, functional signal speed is significantly degraded. Stacking individually packaged DRAM (package-on-package) has had considerable success but the package outline dimension and package height can be excessive. In this paper the authors will introduce a very innovative and very thin 3D package developed specifically for center-bond pad DRAM die. The package assembly methodology promises to remain economical because it requires no special die level process steps and it can utilize the existing package assembly infrastructure. Additionally, data compiled during extensive performance and reliability modeling will be presented along with the results from actual physical qualification testing.|
|Simon McElrea, President
San Jose, CA