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Enabling Packaging Houses to Achieve 3D Integration without Interposers
Keywords: 3D Packaging, Printed Electronics, Stacked Die
The growth of small portable consumer electronics has increased the requirements of creating densely stacked packages with ever decreasing footprints while still increasing storage capacities as well as accessible memory. Traditional approaches to create these packages have included wire-bonding and Package on Package (PoP) as well as through Silicon Via (TSV). All of these methods present a solution to current system requirements, each with its own drawback. This paper will discuss a novel method in which a vertical 3D die stack can be created of similar an in some cases dissimilar die. The final 3D structure of stacked die will present no XY offset between any level of the die stack achieving the smallest possible form factor. This method also eliminates the requirements of creating an interposer for the electrical connection between layers. The final result is a completely vertical die stack with electrical connections drawn on the outside edges of the die stack which adds <400um total in either the X or Y axis of the package. We will discuss required equipment, the best known methods and the optimal materials required to achieve the final product as well as JEDEC reliability data proving package robustness, such as Temperature Cycle, biased-HAST and High Temperature Storage.
Jeff Leal, Advanced Product Development Manager
Vertical Circuits Inc.
Scotts Valley, CA

  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems
  • Technic