Here is the abstract you requested from the DPC_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Micromachined High Density Embedded Capacitor Technologies for Silicon Interposers|
|Keywords: Embedded Capacitor, Micro-machining , Silicon Interposer|
|We describe our work on micromachined, large surface area, thin and high-density capacitor technologies targeted at the growing interest and applications for embedded passive devices in thin silicon interposers. As integrated circuit I/O number, speed and density increase, chip current requirements grow and margins shrink leading to the requirement of large, distributed decoupling capacitance as close to the load as possible. The simple fabrication methods used to form our embedded capacitors can be used to alleviate the increasing demand for low impedance power distribution networks in high-density integrated electronic systems while maintaining required signal integrity through the interposer. We have investigated silicon dioxide-based capacitors of varying oxide thickness, with and without integrated parallel metal Schottky barrier capacitors or pn junction capacitors. These device structures have been fabricated using standard MEMS processing techniques such as DRIE and thermal oxidation to enhance the available surface area and increase capacitance per chip foot-print. We have characterized the performance of the various capacitor structures using both time and frequency response measurements. Time response measurements are performed using a capacitive charge and discharge ringdown test. High frequency (> 1GHz) performance characterization and modeling of these devices has also been performed. In general, measurement results correlate with simulation. We will describe the challenges associated with fabricating, testing and integrating these passive devices. On-going measurement and simulation work that will be reported includes modification of device structures to evaluate the range of achievable capacitance density, minimize leakage current, minimize effective series inductance / resistance, and achieve thinned capacitor structures integrated into our Si interposer technology that incorporates electroplated through-Si vias (TSVs) of varying sizes and densities. The results of these efforts will be presented.|
|Aubrey Beal, Graduate Research Assistant