Abstract Preview

Here is the abstract you requested from the DPC_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Silicon Interposer Creation Using Innovative Ultra-Thin Wafer Handling Solutions
Keywords: innovative debonding, 3D integration, thin wafer handling
Three-dimensional (3-D) wafer stacking technologies are receiving an increasing interest, even if it poses forward new challenges in the development of through silicon vias (TSVs) and thin wafer handling technologies. Several approaches have been developed these years for wafer separation. Even if many examples can be found in literature of the slide-off debonding use for TSVs applications, the thermoplastic materials required for this technique could be limiting for future 3D backside processes. Therefore, innovative room temperature debonding process, including special carrier treatment, has been recently developed to enable a vertical carrier/device separation on a dicing frame at room temperature. The purpose of this paper is to demonstrate the feasibility of this innovative temporary bonding technique and associated equipments. In a first time we have compared 3 temporary materials stability in a short loop process representative of critical backside integration steps. From these results we identify the appropriate material to fit with our face to back applications requiring 90µm thick adhesive and backside processes approaching 200°C. Secondly, we checked impact of the carrier surface treatment on thermal stability. We confirmed that depending on surface treatment, the thermal stability of bonding is impacted, and we identified the treatment enabling to achieve backside processes up to 220°C without observing any interfacial degradation. Finally, we checked the performances in integration of the selected temporary adhesive and carrier from previous studies. In this frame we achieved a full backside via-mid process on test vehicles and fully-functional wafers presenting 70µm heigh micro bumps on their frontside. After providing a description of our integration flow, we show that all bondings successfully passed the chemical and thermal process steps. Electrical measurements of the interposer before and after debonding and cleaning on tape steps finally demonstrate the relevancy of this process for future TSV processings.
Amandine Jouve, Project Leader

  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems